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VME PIO Operations

During programmed I/O (PIO) to the VME bus, software in the CPU loads or stores the contents of CPU registers to a device on the VME bus. The operation of a CPU load from a VME device register is as follows:

  1. The CPU executes a load from a system physical address.

  2. The system recognizes the physical address as one of its own.

  3. The system translates the physical address into a VME bus address.

  4. Acting as a VME bus master, the system starts a read cycle on the VME bus.

  5. A slave device on the VME bus responds to the VME address and returns data.

  6. The VME controller initiates a system bus cycle to return the data packet to the CPU, thus completing the load operation.
A store to a VME device is similar except that it performs a VME bus write, and no data is returned.

PIO input requires two system bus cycles--one to request the data and one to return it--separated by the cycle time of the VME bus. PIO output takes only one system bus cycle, and the VME bus write cycle run concurrently with the next system bus cycle. As a result, PIO input always takes at least twice as much time as PIO output. (For details, see "VME PIO Bandwidth".)

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